;** ################################################################### ;** This code is generated by the Device Initialization Tool. ;** It is overwritten during code generation. ;** USER MODIFICATION ARE PRESERVED ONLY INSIDE INTERRUPT SERVICE ROUTINES ;** ;** Project : junk1 ;** Processor : MC9S08GB60CFU ;** Version : Bean 01.165, Driver 01.00, CPU db: 2.87.177 ;** Datasheet : MC9S08GB60/D Rev. 2.3 12/2004 ;** Date/Time : 10/11/2009, 7:08 AM ;** Abstract : ;** This module contains device initialization code ;** for selected on-chip peripherals. ;** Contents : ;** Function "MCU_init" initializes selected peripherals ;** ;** (c) Copyright UNIS, spol. s r.o. 1997-2006 ;** UNIS, spol s r.o. ;** Jundrovska 33 ;** 624 00 Brno ;** Czech Republic ;** http : www.processorexpert.com ;** mail : info@processorexpert.com ;** ################################################################### INCLUDE MC9S08GB60.inc ; I/O map for MC9S08GB60CFU CODE_SECT: SECTION XDEF MCU_init ;** =================================================================== ;** Method : MCU_init (bean MC9S08GB60) ;** ;** Description : ;** Device initialization code for selected peripherals. ;** =================================================================== MCU_init: ; ### MC9S08GB60 "Cpu" init code ... ; Common initialization of the write once registers ; SOPT: COPE=0,COPT=1,STOPE=0,BKGDPE=1 LDA #$53 STA SOPT ; SPMSC1: LVDF=0,LVDACK=0,LVDIE=0,LVDRE=1,LVDSE=1,LVDE=1 LDA #$1C STA SPMSC1 ; SPMSC2: LVWF=0,LVWACK=0,LVDV=0,LVWV=0,PPDF=0,PPDACK=0,PDC=0,PPDC=0 CLRA STA SPMSC2 ; System clock initialization ; ICGC1: RANGE=1,REFS=0,CLKS1=0,CLKS0=1,OSCSTEN=1 MOV #$4C,ICGC1 ; ICGC2: LOLRE=0,MFD2=1,MFD1=0,MFD0=1,LOCRE=0,RFD2=0,RFD1=1,RFD0=0 MOV #$52,ICGC2 ; ICGTRM: Initialize internal clock trim from a non volatile memory LDA $FFBE STA ICGTRM while0: ; Wait BRCLR 3,ICGS1,while0 ; Common initialization of the CPU registers ; PTASE: PTASE7=0,PTASE6=0,PTASE5=0,PTASE4=0,PTASE3=0,PTASE2=0,PTASE1=0,PTASE0=0 CLR PTASE ; PTBSE: PTBSE7=0,PTBSE6=0,PTBSE5=0,PTBSE4=0,PTBSE3=0,PTBSE2=0,PTBSE1=0,PTBSE0=0 CLR PTBSE ; PTCSE: PTCSE7=0,PTCSE6=0,PTCSE5=0,PTCSE4=0,PTCSE3=0,PTCSE2=0,PTCSE1=0,PTCSE0=0 CLR PTCSE ; PTDSE: PTDSE7=0,PTDSE6=0,PTDSE5=0,PTDSE4=0,PTDSE3=0,PTDSE2=0,PTDSE1=0,PTDSE0=0 CLR PTDSE ; PTESE: PTESE7=0,PTESE6=0,PTESE5=0,PTESE4=0,PTESE3=0,PTESE2=0,PTESE1=0,PTESE0=0 CLR PTESE ; PTFSE: PTFSE7=0,PTFSE6=0,PTFSE5=0,PTFSE4=0,PTFSE3=0,PTFSE2=0,PTFSE1=0,PTFSE0=0 CLR PTFSE ; PTGSE: PTGSE7=0,PTGSE6=0,PTGSE5=0,PTGSE4=0,PTGSE3=0,PTGSE2=0,PTGSE1=0,PTGSE0=0 CLR PTGSE ; ### Init_TPM init code ; TPM1SC: TOF=0,TOIE=0,CPWMS=0,CLKSB=0,CLKSA=0,PS2=0,PS1=0,PS0=0 CLR TPM1SC ; Stop and reset counter LDHX #$00 STHX TPM1MOD ;/* Period value setting */ LDA TPM1SC ; Overflow int. flag clearing (first part) ; TPM1SC: TOF=0,TOIE=1,CPWMS=0,CLKSB=0,CLKSA=1,PS2=1,PS1=0,PS0=1 MOV #$4D,TPM1SC ; Int. flag clearing (2nd part) and timer control register setting ; ### Init_GPIO init code ; PTFDD: PTFDD0=1 BSET $00,PTFDD ; ### CLI ; Enable interrupts RTS ;** =================================================================== ;** Interrupt handler : LEDtimer ;** ;** Description : ;** User interrupt service routine. ;** Parameters : None ;** Returns : Nothing ;** =================================================================== XDEF LEDtimer LEDtimer: LDA #$01 ; Mask for bit 1 EOR PTFD ; Invert the first bit of PTFD STA PTFD ; Write the result to PTFD LDA TPM1SC ; Read the register BCLR TPM1SC_TOF,TPM1SC ; and clear the overflow flag RTI ; end of LEDtimer ;** =================================================================== ;** Interrupt handler : ClkMon ;** ;** Description : ;** User interrupt service routine. ;** Parameters : None ;** Returns : Nothing ;** =================================================================== XDEF ClkMon ClkMon: ; Write your interrupt code here ... RTI ; end of ClkMon ; Initialization of the CPU registers in FLASH ; NVPROT: FPOPEN=1,FPDIS=1,FPS2=1,FPS1=1,FPS0=1 ORG NVPROT DC.B $FF ; NVOPT: KEYEN=0,FNORED=1,SEC01=1,SEC00=0 ORG NVOPT DC.B $7E XREF _Startup ; Interrupt vector table UNASSIGNED_ISR: EQU $FFFF ; unassigned interrupt service routine ORG $FFCC ; Interrupt vector table _vect: DC.W UNASSIGNED_ISR ; Int.no. 25 Vrti (at FFCC) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 24 Viic1 (at FFCE) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 23 Vatd1 (at FFD0) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 22 Vkeyboard1 (at FFD2) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 21 Vsci2tx (at FFD4) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 20 Vsci2rx (at FFD6) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 19 Vsci2err (at FFD8) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 18 Vsci1tx (at FFDA) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 17 Vsci1rx (at FFDC) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 16 Vsci1err (at FFDE) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 15 Vspi1 (at FFE0) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 14 Vtpm2ovf (at FFE2) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 13 Vtpm2ch4 (at FFE4) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 12 Vtpm2ch3 (at FFE6) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 11 Vtpm2ch2 (at FFE8) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 10 Vtpm2ch1 (at FFEA) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 9 Vtpm2ch0 (at FFEC) Unassigned DC.W LEDtimer ; Int.no. 8 Vtpm1ovf (at FFEE) Used DC.W UNASSIGNED_ISR ; Int.no. 7 Vtpm1ch2 (at FFF0) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 6 Vtpm1ch1 (at FFF2) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 5 Vtpm1ch0 (at FFF4) Unassigned DC.W ClkMon ; Int.no. 4 Vicg (at FFF6) Used DC.W UNASSIGNED_ISR ; Int.no. 3 Vlvd (at FFF8) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 2 Virq (at FFFA) Unassigned DC.W UNASSIGNED_ISR ; Int.no. 1 Vswi (at FFFC) Unassigned DC.W _Startup ; Int.no. 0 Vreset (at FFFE) Reset vector END ;** ################################################################### ;** ;** This file was created by UNIS Processor Expert 2.98 [03.80] ;** for the Freescale HCS08 series of microcontrollers. ;** ;** ###################################################################