Please look this over carefully and  if you
see any mistakes please let me know.

Paul Lamar
Hello Paul, Tracy and Mark,
4000-series CMOS IC's are very vulnerable to static electricity.
I suggest that you must ensure that there are safeguards in place to
prevent the IC from getting "zapped" during load dumps or other electrical
system events.

It would be much preferable to use mil-spec components, such as a  54HCU04.
 This is a high-speed unbuffered TTL-level CMOS hex inverter that  can be
pressed into service as an open-loop amplifier.

The INPUTS to any unused inverters must be connected to either Vdd or
GND/Vss to prevent high-frequency oscillations/instability.

The schematic does not have any protection for the input to the gate.   I
suggest 1k to 10k Ohms.
There are no clamping diodes.  These are a must.  1N914/1N4148  diodes
would be sufficient; one from the Vdd rail to the input (cathode to Vdd)
 and
one from the input to GND/Vss (anode to GND/Vss).

There is some overshoot on the 'scope display.  This is due to the
inductance of the wiring not being damped with resistors in the signal
 path.
Low-value resistors (say, 47 or 51 Ohms) at the input to the next  stage
will
help a great deal to eliminate the overshoot.

Regards,
Steve in Orlando

I'll turn over all the PC board design work to you Steve if you want it.
Here is the latest schematic and board design.

Paul Lamar


Circuit protection against high voltage can be broken into (at least)
two categories..  ESD events, and normal operation..

ESD can be in the thousands of volts, but is usually a fairly small
amount of total energy.  ESD events aren't typically repetitive in the
way that normal operation can be.

Modern CMOS IC's are relatively well protected from a variety of ESD
and spurious voltages.  Often each pin is buffered.  The buffer gates
usually employ much more robust devices than internal logic.  As well,
the buffer often includes ESD stacks connected to Vdd and Vss.
Largely this is done to make manufacturing of the devices and
installation of the devices in an application easier.  I work at a
manufacturer of DRAM chips and have my hands on them every day.  While
we employ fairly strict ESD safeguards for the chips that actually
make it out the door, I regularly handle chips at my desk and while
walking around a regular office environment and have never observed a
device stop working because of ESD damage.  Even so, chips that end up
at my desk are usually scrapped to avoid sending out walking-wounded
(parts that are damaged in non-obvious ways).

Normal operation can be considered as a somewhat separate situation.
Analysis of the circuit should be done to identify what the voltage
will be at each node.  Consider the reactance of each component of the
circuit.  It's possible to calculate most of this stuff, SPICE can do
that.  However, it's also possible and maybe more important to use
some rules of thumb to figure out what's likely going on.

All that said, I agree that 4000 series IC's might not be the best
choice for application in an experimental ignition systems.  I haven't
found good data describing whether there are diodes built into each
pin like in other logic chips.
The data sheets usually say the logic input voltage can go as high as
0.5V above Vdd.  I would guess that driving an input higher than that
causes the ESD stack to forward bias which may effect circuit
operation.  Driving much higher than that can latch up parts of the
circuit.  Exposing the circuit to continuous, repeated voltage
excursions (as in operating the device in an out-of-spec way) can
cause damage.


Regards,

Matt-