This is what put the ARM over the top for me. To my knowledge the ARM is the only CPU
with this level of sophistication for the interrupt system.
The Ti LM3S9B95 controller includes the ARM Latched Nested Vectored Interrupt
Controller (NVIC). The NVIC and Cortex-M3 prioritize and handle all
exceptions in Handler Mode.
1.The processor state is automatically stored to the stack on an exception and
automatically restored from the stack at the end of the Interrupt Service
Routine (ISR). The interrupt vector is fetched in parallel to the state
saving, enabling efficient interrupt entry.
2. The processor supports tail-chaining, meaning that back-to-back interrupts
can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and
53 interrupts. [Half the pins :)]
3.Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles
with tail-chaining External non-maskable interrupt signal (NMI) available
for immediate execution of NMI handler for safety critical applications
4. Dynamically reprioritizable interrupts Exceptional interrupt handling via
hardware implementation of required register manipulations
Back in the old 6502 days we had to PUSH all registers used on the stack when an
interrupt came in and POP them off the stack on return from interrupt.
I designed and built my own 8 bit interrupt controller for the 6502 SuperKim.
Eight latched prioritized interrupts. Latches are individually resettable
under software control. The rising edge of the interrupt pulse sets the
latch. Absolutely essential for implementing highly useful real
time mechanical control systems. I like to think Acorn probably read about this
back in the late 70's and decided to incorporate the idea into the predecessor of the
ARM :)
Here is the schematic. It interfaced to the computer with just one 6522 8 bit
parallel port.
Paul Lamar
--
The Rotary Engine News Letter. Powered by Linux.
ACRE NL web site.
http://www.rotaryeng.net
You Tube key word PaulLamar2
Copyright 1998-2012 All world wide rights reserved.
