Subject: simple 8051 interrupts
From: rotaryeng
Date: 8/17/2012, 8:25 AM
To: AAAA Put this in the To box 

Interrupt Priorities

It is not possible to forsee when an interrupt request will arrive. If
several interrupts are enabled, it may happen that while one of them is in
progress, another one is requested.  In order that the microcontroller knows
whether to continue operation or meet a new interrupt request, there is a
priority list instructing it what to do.

The priority list offers 3 levels of interrupt priority:

1. Reset! The apsolute master. When a reset request arrives, everything is stopped
and the microcontroller restarts.

2. Interrupt priority 1 can be disabled by Reset only.

3. Interrupt priority 0 can be disabled by both Reset and interrupt priority 1.
The IP Register (Interrupt Priority Register) specifies which one of existing
interrupt sources have higher and which one has lower priority. Interrupt priority is
usually specified at the beginning of the program.

According to that, there are several possibilities:

• If an interrupt of higher priority arrives while an interrupt is in progress, it
will be immediately stopped and the higher priority interrupt will be executed first.

• If two interrupt requests, at different priority levels, arrive at the same time
then the higher priority interrupt is serviced first.

• If the both interrupt requests, at the same priority level, occur one after
another, the one which came later has to wait until routine being in progress ends.

• If two interrupt requests of equal priority arrive at the same time then the
interrupt to be serviced is  selected according to the following priority list:

1.External interrupt INT0
2.Timer 0 interrupt
3.External Interrupt INT1
4.Timer 1 interrupt
5.Serial Communication Interrupt

IP Register (Interrupt Priority)
The IP register bits specify the priority level of each interrupt.
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This is why it will keep it simple and use one CPU per rotor.

Paul Lamar

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